1. Field of the Invention
The present invention relates in general to phase locked loop circuits and more particularly, to a method and apparatus for providing a flexible phase locked loop system that is compatible with a variety of standards.
2. Description of the Related Art
In the filming industry, it is desirable to synchronize each film frame or video frame to the corresponding audio samples, so that the appropriate speech, music and/or sound effects may be matched with the corresponding action during playback.
To accomplish this, the frames are counted and provided to a master circuit which runs the projector and the audio systems at the same speed. As shown in FIG. 1A, the film is typically run at 24 frames per second. The audio signals are typically sampled at 48 kHz. For this example, each of the frames have 2,000 corresponding audio samples. The master circuit typically employs a phase locked loop (PLL) system 10 (FIG. 1B) comprising a phase-frequency detector (PFD) 12, a voltage-controlled oscillator (VCO) 14, a divide-by-A circuit 16 and a divide-by-B circuit 18. The frequency divider circuits 16 and 18 are used in the feedback loops of the PLL so that frequencies higher than that of the input clock signal can be generated. The output of the VCO 14 is provided as a first output signal for internal operations of the master circuit. The output of the VCO 14 is also provided to the divide-by-A circuit 16, which subsequently generates a second output signal that is typically used to synchronize the video information with audio information (which typically operates at 48 kHz). The value of A is determined by the ratio of the master clock frequency to the audio frequency to be synchronized to. For example, if the audio frequency is 48 kHz, and the master clock frequency is 12.288 MHz, A=256.
The second output signal is also provided to the divide-by-B circuit 18. The divide-by-B circuit 18 generates a feedback signal that is provided to the PFD 12. The value of B is determined by a ratio of the audio frequency to be synchronized to and the frame clock frequency. For example, if the audio frequency is 48 kHz and the frame clock frequency is 24 Hz, the value of B will be 2,000. The PFD 12 receives input signals from a frame clock and compares the phase/frequency of the input signals with the phase/frequency of the feedback signal. The PFD 12 produces a control voltage which is a function of the difference (error) between the input signal and the feedback signal. The PFD 12 presents the control voltage to a loop filter 14, which filters the output voltage of the PFD 12 and subsequently provides the filtered output voltage to the VCO 16 to adjust the frequency of the output signal. After some time as determined by the frequency response of the loop, the PLL system 10 locks onto the input clock signal and presents an output having a stable frequency and phase.
However, such an approach requires a substantially lengthy period for the PLL system 10 to lock onto the input clock signal, because the input clock signal operates at a low frequency, typically 24 Hz. In addition, the PLL system 10 is susceptible to noise conditions such as power supply fluctuations, etc. To avoid the slow response time and instability of such a PLL system, a higher input clock frequency is used. A typical frequency is the horizontal frequency as established by the National Television Systems Committee (NTSC). Although such an approach overcomes the slow response time and instability problems of the previous technique, it cannot provide the flexibility of accommodating a variety of video formats like the Phase Alternating Line (PAL), Sequential Couleur avec Memoire (SECAM) and NTSC.
Accordingly, there is a need in the technology for providing a stable PLL system that provides a fast response time, while providing flexibility and compatibility with a variety of video standards.
A stable and flexible synchronization system and method are disclosed. The method comprises (a) selecting to receive one of a plurality of external clock signals; (b) detecting a difference between an internal clock signal and the selected one of a plurality of external clock signal and generating a first control signal representing the difference; (c) determining if the first control signal has a first value that is within a predetermined range; (d) if so, calculating a second value representing an absolute value of a difference between a current value of the first control signal and a previous value of the first control signal, otherwise repeating (c); (e) determining if the second value is less than a third value; (f) if so, resetting the output signal upon receipt of an edge of said selected one of the plurality of external clock signals, otherwise repeating (c); (g) determining if a timing difference between the output signal and the selected one of the plurality of external clock signals is substantially zero; (h) if so, issuing a signal indicative of synchronization, otherwise repeating (c).